搜索资源列表
four_adder
- 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
f_adder
- 全加器， 全加器-Full-adder, full adder, full adder
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
fulladder
- full adder. dai jinwei de liangwei quan jiaqi-fulladder
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
addersandsubtractors
- this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
ex15
- 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
cadence_multi-threshold
- linux下(fedora版本)的cadence中编译4位全加器的实现, 在不同的阈值电压调解下观察点路的总体power和速度,以及逻辑的正确性. 可能会用到NCSU的FREEPDF工具包-this is a package of three projects, low-vth, high-vth, and optimum architecture vth four bit full adder design. In the environment of Cadence and then sim
quanjiaqi
- 建立了基于matlab语言的四位全加器仿真模型，通过了系统验证。-Matlab language is established based on four full adder simulation model, verified by the system.
adder_fa4bit
- 4 bit full adder verilog code n test bench
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
Full-Adder
- Full Adder to add 4 bits of input
4bit-adder_verilog
- 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
four_bit-full-adder
- 四位的全加器，包含8421码与2421码的相互转换，2421码的加法修正-Four of the full adder, including 8421 yards and 2421 yards of the conversion, the addition of amendments to 2421 yards
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
Four-bit-full-adder
- 四位全加器，是自己编写的，如有错误，请原谅-I have written four full adder, is subject to error, please forgive
2-bit-full-adder-master
- full adder 4 bit one you